Adder-subtractor device and method for making the same

ABSTRACT

An adder-subtractor includes a jth device for each bit position j for computing a result for an expression ±a 0  ±a 1 , where a 0  and a 1  are binary numbers. The jth device is from a group of devices, the group being defined by formulas using integer parameters k, p 0 , p 1 , t, x 0 , x 1 , y 0 , and y 1 , each of the parameters having a integer value that is 0 or 1. The jth device includes a line carrying an input a 1j  representing a jth digit of the a 1  number. The jth device further includes a line carrying an input w 1j  =1-y 1  when s 1  =1-x 1  and if a previous bit position of the a 1  number is 1, and w 1j  =y 1  when s 1  =1-x 1  and there is no 1 on previous bit position. A plurality of switches, between the lines, direct to the forward output F out  a bit value, according to one of said formulas: 
     
         F.sub.out =(1-p.sub.k)(s.sub.k ⊕x.sub.k)(w.sub.kj 
    
      ⊕y k )⊕a kj  ⊕t 
     
         if 
    
     
         p.sub.0 (s.sub.0 ⊕x.sub.0)⊕(1-p.sub.0)(s.sub.0 
    
      ⊕x 0 )(w 0j  ⊕y 0 )⊕a 0j  =p 1  (s 1  ⊕x 1 )⊕(1-p 1 )(s 1  ⊕x 1 ) (w 1j  ⊕y 1 )⊕a 1j , 
     the plurality of switches, also for directing the forward input F in  to the output c j  such that the output is according to another of said formulas: 
     
         c.sub.j =(1-p.sub.0)(s.sub.0 ⊕x.sub.0)(w.sub.0j 
    
      ⊕y 0 )⊕a 0j  ⊕(1-p 1 )(s 1  ⊕x 1 )(w 1j  ⊕y 1 )⊕a 1j  ⊕(1-(s k  ⊕x k )p k )(s 1-k  ⊕x 1-k )p 1-k  ⊕t⊕F in  ⊕p 0  ·p 1  (s 0  ⊕x 0 )(s 1  ⊕x 1 )((w 0j  ⊕y 0 )⊕(w 1j  ⊕y 1 ) ⊕(w 0j  ⊕y 0 )(w 1j  ⊕y 1 )). 
     The adder-subtractor can also have the plurality of switches directing the forward input F in  to the forward output F out  if 
     
         p.sub.0 (s.sub.0 ⊕x.sub.0)⊕(1-p.sub.0)(s.sub.0 
    
      ⊕x 0 )(w 0j  ⊕y 0 )⊕a 0j  ≠p 1  (s 1  ⊕x 1 )⊕(1-p 1 )(s 1  ⊕x 1 )(w 1j  ⊕y 1 )⊕a 1j .

CROSS-REFERENCE TO RELATED APPLICATIONS

This patent application is a continuation-in-part of the patentapplication Ser. No. 08/123,731, now abandoned, filed Dec. 1, 1993.

FIELD OF THE INVENTION

This invention pertains to calculating devices. More particularly, thepresent invention involves devices and methods relating to anadder-subtractor. The adder-subtractor can be of the electronic,optical, mechanical, hydraulic, or pneumatic type.

BACKGROUND OF THE INVENTION

There are many kinds of adders and subtractors known in the prior art.Some are analog devices, but for handling many digits with speed andaccuracy, the primary focus has turned to digital signal-processingdevices. Many kinds of digital adders and subtractors have been exploredin the prior art, as described for example in Hill, Fredrick J. andPeterson, Gerald R., Introduction to Switching Theory and Logic Design,3rd ed. (Wiley 1981).

Those known digital adders and subtractors rely on sequentialprocessing. That is, integers being added and subtracted are digitalizedinto representations having a number of bits in bit positions. For eachbit position there are levels of gaging, whereby a result computed byeach bit position device is fed into the next bit position device in acascade of devices: "The addition process may thus be carried out onedigit at a time, starting with the least significant digit." SwitchingTheory at page 176. (This gives rise to the notion of a "carry"propagation from one bit position to the next--a signal output from thedevice computing the first bit to the device computing the next bitposition.)

A consequence of such prior art designs processing is slowed by thelevels of gaging and the sequence of processing used to add and subtractintegers represented with more than one bit. In applications requiringspeed, the slowness of the sequential processing is a seriousconsequence.

Also, according to Switching Theory at pages 180-181, "there are,unfortunately, no simple rules or completely specified procedures forfinding such designs." Thus, it is difficult to design device, in theabsence of a generalized method.

Further, the adders and subtractors of the known prior art must eachfind a way to deal with the respective signs of the integers. Forexample, the sign at the first number can be treated as positive and thesign at the second number can be used in specifying that there isaddition or subtraction of the two numbers. Often the handling of thesigns of the respective integers limits the flexibility of the deviceand adds delay to the processing.

Additionally, a design in the known prior art that can be implemented inone media, say, electrical, may be unworkably difficult to implement inanother media, say, optical. Limited flexibility is another problem inthe prior art.

SUMMARY OF THE INVENTION

Accordingly, several representative objects and advantages of myinvention are as follows:

An object of the present invention is to provide a fast apparatus, andmethods related thereto, for digital addition and subtraction ofintegers.

Another object of the present invention is to provide an apparatus, andmethods related thereto, that handles all bit positions of the integerssimultaneously to ensure a short time period for performing arithmeticaloperations.

Yet another object of the present invention is to provide an apparatus,and methods related thereto, that combines addition and subtraction inthe handling of the signs for the respective integers.

Yet another object of the present invention is to permit a minimalnumber of interconnections and relations between the parts of theadder-subtractor devices, and to allow for different species (havingdifferent interconnections and relations between the parts).

Yet another object of the present invention is to provide a simpleadder-subtractor in which switches can be set up only once to obtain anaddition or subtraction result with as little as one clock cycle.

Still another object of the present invention is to provideadder-subtractor device designs that can be constructed in electronic,optical, mechanical, hydraulic, pneumatic, and other equivalentembodiments.

A further object of the present invention is to provide anadder-subtractor that can be used as a counter.

These and other objects apparent from the disclosure are accomplishedwith the invention of a class of adder-subtractor devices, along withthe methods for making and using the class of devices. The class can beconsidered a genus of which each species can be considered a part of theinstant invention.

More particularly, the adder-subtractor device includes a jth device foreach bit position j (any number of j devices) for computing a result cfor an expression ±a₀ ±a₁, where a₀ and a₁ are binary numbers. The jthdevice is from a group of devices defined by formulas using integerparameters k, p₀, p₁, t, x₀, x₁, y₀, and y₁, each of the parametershaving an integer value that is zero or one. The jth device includes aline carrying an input s₀. The input s₀ represents x₀ if the sign at thea₀ number in the expression is positive, and s₀ represents 1-x₀ if thesign at the a₀ number in the expression is negative. The jth device alsoincludes a line carrying an input a_(0j) representing a jth digit of thea₀ number. Further, there is a line carrying an input s₁ representing x₁if the sign at the a₁ number in the expression is positive, andrepresenting 1-x₁ if the sign at the a₁ number in the expression isnegative. Further, the jth device includes a line carrying an inputa_(1j) representing a jth digit of the a₁ number. The jth device furtherincludes a line carrying an input w_(0j) =1-y₀ if s₀ =1-x₀ and if aprevious bit position of the a₀ number is 1, and w_(0j) =y₀ if s₀ =1-x₀and if there is no 1 at a previous bit position. The jth device furtherincludes a line carrying an input w_(1j) =1-y₁ if s₁ =1-x₁ and if aprevious bit position of the a₁ number is 1, and w_(1j) =y₁ if s₁ =1-x₁and if there is no 1 at a previous bit position. The jth device furtherincludes at least one line carrying a forward input F_(in), at least oneline carrying a forward output F_(out), and a line carrying an outputc_(j) representing a jth digit of the result c from computing theexpression ±a₀ ±a₁. Further, between the previously mentioned lines,there is a plurality of switches, switching gates, or an equivalentmeans for directing the forward input F_(in) to the output c_(j)according to one of the formulas: ##EQU1## the plurality of switches orequivalent means also for directing a bit value to the forward outputF_(out) according to an other of the formulas:

    F.sub.out =(1=p.sub.k)(s.sub.k ⊕x.sub.k)(w.sub.kj ⊕y.sub.k)⊕a.sub.kj ⊕t

    if

    p.sub.0 (s.sub.0 ⊕x.sub.0)⊕(1-p.sub.0)(s.sub.0 ⊕x.sub.0)(w.sub.0j ⊕y.sub.0)⊕a.sub.0j =p.sub.1 (s.sub.1 ⊕x.sub.1)⊕(1-p.sub.1)(s.sub.1 ⊕x.sub.1)(w.sub.1j ⊕y.sub.1)⊕a.sub.1j.

The adder-subtractor can also have the plurality of switches, gates, orequivalent means direct the forward input F_(in) to the forward outputF_(out) if

    p.sub.0 (s.sub.0 ⊕x.sub.0)⊕(1-p.sub.0)(s.sub.0 ⊕x.sub.0)(w.sub.0j ⊕y.sub.0)⊕a.sub.0j ≠p.sub.1 (s.sub.1 ⊕x.sub.1)⊕(1-p.sub.1)(s.sub.1 ⊕x.sub.1)(w.sub.1j ⊕y.sub.1)⊕a.sub.1j.

The present invention is fast because the plurality of switches fordirecting can have all switching therein set essentially simultaneously,rather than sequentially. Thus, integer addition and subtraction can behandled with as little as one clock cycle.

The present invention has an improved manner for handling the signs ofthe respective integers because the plurality of switches for directingcombines the two integers (negative, positive, or 0's) and handles thesigns at the integers essentially simultaneously.

The present invention provides for design ease because a generalizedmethod of designing adder-subtractor devices is provided by the formulassuch that species can be designed as versions of the formulas simplifiedto cover particular applications or situations.

The present invention also is more flexible because designs can beconstructed in electronic, optical mechanical, hydraulic, or pneumaticembodiments.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram an adder-subtractor according to the presentinvention.

FIG. 2 is a diagram of a βON switch.

FIG. 3 is a diagram of 0ON and 1ON switches.

FIG. 4 is a diagram of an Λ switch.

FIG. 5 is another diagram of an Λ switch.

FIG. 6 is a diagram of a V switch.

FIG. 7 is another diagram of a V switch.

FIG. 8 is a diagram of an 0X0 switch.

FIG. 9 is another diagram Λ switches.

FIG. 10 is a diagram of a species of the device diagramed in FIG. 1.

FIG. 11 is a diagram of the species of the device diagramed in FIG. 10in a configuration for handling multiple digits.

FIG. 12 is a diagram of an alternative embodiment of the speciesdiagramed in FIG. 10.

FIG. 13 is a diagram of the alternative embodiment of the speciesdiagramed in FIG. 12 in a configuration for handling multiple digits.

DETAILED DESCRIPTION OF THE INVENTION

In the present invention, positive and negative binary integers arerepresented as follows: The integer zero is denoted by "(0)".

For non-zero integers, the sign of the integer can be designated by themost significant bit (which can be represented in parentheses), i.e.,"the sign bit." For example, if the sign bit is (0) the number isnonnegative, and if the sign bit is (1) the number is negative. As afurther example, consider the number +1 represented by two digits: (0)1.The first bit (0) designates the sign of the number such that a (0)indicates a nonnegative sign in contrast to the alternative of a (1)which would indicate a negative sign. The second bit 1 designates thevalue of the number. A value for a number is not changed by repeatingthe sign bit to the left of the number. Thus, with the notation usedherein, (0)01=(0)1. The left side of the immediately forgoing equalityis an extended form of the right side of the equality because the second0 on the left side merely repeats the sign for the number having a valueof 1.

More particularly, consider the two examples in Example 1 in which "a"with a subscript represents a respective binary digit of a number, asdoes "b" with a subscript.

EXAMPLE 1

    (0)a.sub.4 a.sub.3 a.sub.2 a.sub.1 =(0)00a.sub.4 a.sub.3 a.sub.2 a.sub.1

    and

    (1)b.sub.3 b.sub.2 b.sub.1 =(1)1111b.sub.3 b.sub.2 b.sub.1.

Both examples in Example 1 illustrate that all but one of the sameleading bits can be ignored when defining the sign and the value of amultidigit number. That is, in a multidigit number, leading zeros can bereduced to one bit (0), and leading ones can be reduced to (1) to get acompact form of the integer. (Compact integers contain less digits andoccupy less memory space.)

An integer can be represented as a two's complement in m₋₋ bits in anextension of the compact form through repetition the sign bit to themth-position. This is illustrated in the two examples of Example 2.

EXAMPLE 2

    (1)=(1)11111

    and

    (0)=(0)00000.

An operational symbol for a sum ⊕ can be defined as follows for bits x,y=0 or 1:

x⊕y=|x-y| is equal to a distance between x and y. Accordingly, thefollowing properties exist:

    x⊕y=y⊕x=remainder from (x+y) divided by 2;

    NOT x=1⊕x=|1-x|=1-x;

    (x⊕y)⊕u=x⊕(y⊕u)=x⊕y⊕u;

among three bits x', y', and z' two are identical, and the sum x'⊕y'⊕z'is equal to the remaining bit. Example 3 below shows these properties

EXAMPLE 3

    0⊕0=1⊕1=0;

    NOT1=1-1=0;

    NOT0=1⊕0=1-0=1;

    x'=1, y'=0, z'=1, x'⊕y'⊕z'=y'=0;

    NOT(NOT x)=1-NOT x=1-(1-x)=x;

An opposite integer is defined by the equality b=-a: b and -a areopposite integers. However, the opposite to number zero to zero, i.e.,-(0)=(0).

Opposite integers can be represented (see Equation 1 below) based on thefollowing assumptions: a=(a_(n+1))a_(n), . . . , a₁ ≠0 and at least onedigit in the sequence a_(n), . . . , a₁ is equal to 1; if theassumptions are not satisfied, then the form of the integer is extended.In the two examples in Example 4, the form of the integer represented onleft side of each equality does not satisfy the assumption. Therefore,the form of the integer is extended as shown on the right side of eachequality.

EXAMPLE 4

    (1)000=(1)1000

    and

    (1)=(1)1.

An opposite numbers procedure can be defined as follows. Given aninteger a, Equation 1 defines the bits of an integer b which is oppositeto a, with "opposite" being defined by the equality b=-a, except forzero, as mentioned above.

For a nonzero integer a=(a_(n+1))a_(n) . . . a₁ with 1 among the digitsin the sequence a_(n) . . . a₁, and a bit a₀ =0, if at some bit positionp≧1 the digit a_(p) =1 and bit a_(r) =0 for r=p-1, . . . , 0, then thedigits of the opposite number b=(b_(n+1))b_(n) . . . b₁ are defined asshown by Equation 1. ##EQU2##

In other words, to define the bits of a nonzero integer b which isopposite to a nonzero integer a, the bits a_(n+1) . . . a₁ aretransformed so that the bits b_(j) at j=p, . . . , 1 are identical thebits a_(j), and the bits b_(j) at j=n+1, . . . , p+1 are different thanthe bits a_(j).

Example 5 illustrates how the transformation can be carried out.

EXAMPLE 5

    a=(0)110100, b=-a=(1)001100;

    n+1=7, p=3;

    a=(0)1, b=-(0)1=(1)1=(1);

    n+1=2, p=1;

    a=(1)=(1)1, b=-(1)1=(0)1;

    n+1=2, p=1;

    (0)1000=8, -8=-(0)1000=(1)1000=(1)000 compact form.

Opposite numbers procedure can be presented in a following equivalentform. For any integer a=(a_(n+1))a_(n) . . . a₁ and a bit position j(n+1≧j≧1), define a parameter w_(j) as follows: w_(j) =1 if there is aprevious position p (j-1≧p≧1) such that a_(p) =1; otherwise w_(j) =0.For example, w₁ =0 because does not exist position p such that(1-1≧p≧1), and further w₂ =a₁. In other words, w_(j) (n+1≧j≧2) is equalto a maximal digit a_(j) from previous bit positions j' (j-1≧j'≧1). Whenb=-a, then b=(b_(n+2))b_(n+1) b_(n) . . . b₁ and b_(j) =a_(j) ⊕w_(j)(n+2≧j≧1), assuming that a_(n+2) =a_(n+1), w_(n+2) =w_(n+1) and(b_(n+2)) is a sign bit.

Note that unlike a complement procedure in the known prior art, whichuses more than one clock cycle, opposite numbers procedure can be doneduring the one clock cycle for addition-subtraction.

Operations on the integers can be considered in the range or out of therange of an adder-subtractor device. Given any two binary integers a₀and a₁ which have following compacted or extended representations intwo's complement in q-bits, (q≧2): ##EQU3## The integers a₀ and a₁ arein the range of the adder-subtractor if the following is true:

    -(2.sup.q-1)≦a.sub.0, a.sub.1 ≦(2.sup.q-1)-1 in a decimal system, or

    (1.sub.q)0.sub.q-1 . . . 0≦a.sub.0, a.sub.1 ≦(0.sub.q)1.sub.q-1 . . . 11 in a binary system.

To calculate a result for an arithmetic expression like ±a₀ ±a₁, achoice is made as to which digit (0 or 1) is used to designate the signin the expression of an integer ±a₀ ±a₁. If in the above expression atthe integer a₀ there is a plus sign before the a₀, i.e., +a₀, then thereis a nonnegative integer parameter such that s₀ =x₀ =0. If instead thereis a negative sign, i.e., -a₀, then s₀ =1-x₀ =1. Also, if instead at theinteger a₁ there is plus sign, i.e., +a₁, then there is a nonnegativeinteger parameter such that s₁ =x₁ =0. If instead there is a negativesign, i.e., -a₁, then s₁ =1-x₁ =1.

Accordingly, for an arithmetic expression like ±a₀ ±a₁, there are fourcases of sign combinations for the integers: ##EQU4##

To obtain digits resulting from computing ^(C) s₀ s₁ =±a₀ ±a₁, thefollowing approach is used. In general, to begin, the integers a₀ and a₁are in a compact form: ##EQU5## Let m=maximum{k,n}. Construct extendedforms of a₀ and a₁ to the m+2 position as follows: a₀=(a_(0m+2))a_(0m+1) a_(0m) . . . a₀₁, with a_(0m+2) =a_(0k) as a signbit; a₁ =(a_(1m+2))a_(1m+1) a_(1m) . . . a₁₁, with a_(1m+2) =a_(1n) as asign bit. Therefore, c=±a₀ ±a₁ =(c_(m+2))c_(m+1) c_(m) . . . c₁. Nextthe integer c can be reduced to a compact form. In making anadder-subtractor, assume that m=q (q≧2) is constant for all integers.That is, assume that input integers a₀ and a₁ are in an extended form.

Accordingly, given two input binary integers a₀ and a₁ having followingrepresentations: ##EQU6## and an input sign at each of the integers inan expression ^(C) s₀ s₁ =±a₀ ±a₁, the output result is ^(C) s₀ s₁=(c_(q+2))c_(q+1) c_(q) . . . c₁. Another way of stating the forgoing isas follows:

    .sup.C s.sub.0 s.sub.1 =±a.sub.0 ±a.sub.1 =±(a.sub.0q)a.sub.0q a.sub.0q a.sub.0q-1 . . . a.sub.01 ±(a.sub.1q)a.sub.1q a.sub.1q a.sub.1q-1 . . . a.sub.11.

The result ^(C) s₀ s₁ is given as shown in Example 6.

EXAMPLE 6

    ______________________________________                                        If bits C.sub.q+2 C.sub.q+1                                                                            C.sub.q                                                                              then integer c is                                     0         0      0      positive in range                                     0         0      1      positive overflow                                     0         1      0      positive overflow                                     1         1      0      negative underflow                                    1         1      1      negative in range.                            ______________________________________                                    

The result ^(C) s₀ s₁ is completely correct, but as with machines in theknown prior art, sometimes there are too many digits produced from thecomputing (i.e., there is positive overflow or negative underflow in amachine doing the computing).

As shown in Example 6, if c_(q+1) and c_(q) are different, then theinteger c is out of the range of the adder-subtractor. The range is asfollows:

-(2^(q-1))≦a₀, a₁ ≦(2^(q-1))-1 in a decimal system,

(1_(q))0_(q-1) . . . 0₁ ≦a₀, a₁ ≦(0_(q))1_(q-1) . . . 1₁ in a binarysystem,

-2^(q) ≦c≦2^(q) in a decimal system,

(1_(q+1))0_(q) . . . 0₁ ≦c≦(0_(q+2))1_(q+1) 0_(q) . . . 0₁ in a binarysystem.

Turning from the handling of all digits to the handling of a j digit,FIG. 1 is a diagram of an adder-subtractor device 2 according to thepresent invention. The adder-subtractor device 2 includes a jth device 4for each bit position j for computing a result for an expression ±a₀±a₁, where a₀ and a₁ are binary numbers. The jth device 4 is from agroup of devices, the group being defined by formulas (set forth below)using integer parameters k, p₀, p₁, t, x₀, x₁, y₀, and y₁, each saidparameter having a nonnegative integer value that is less than two. Thatis, each said parameter has a value of 0 or 1.

Each jth device 4 includes a line 6 carrying an input s₀ representing x₀if the sign at the a₀ number in the expression is positive, andrepresenting 1-x₀ if the sign at the a₀ number in the expression isnegative. The jth device 4 also includes a line 8 carrying an inputa_(0j) representing a jth digit of the a₀ number. Further, the jthdevice 4 includes a line 10 carrying an input s₁ representing x₁ if thesign at the a₁ number in the expression is positive, and representing1-x₁ if the sign at the a₁ number in the expression is negative.Additionally, the jth device 4 includes a line 12 carrying an inputa_(1j) representing a jth digit of the a₁ number.

The jth device 4 further includes a line 14 carrying an input w_(0j)=1-y₀ if s₀ =1-x₀ and if a previous bit position of the a₀ number is 1,and w_(0j) =y₀ if s₀ =1-x₀ and there is no 1 on a previous bit position.The jth device further includes a line 16 carrying an input w_(1j) =1-y₁if s₁ =1-x₁ and if a previous bit position of the a₁ number is 1, andw_(1j) =y₁ if s₁ =1-x₁ and if there is no 1 on a previous bit position.

In any case, the jth device 4 also includes at least one line 18carrying a forward input F_(in) ; at least one line 20 carrying aforward output F_(out) ; and a line 22 carrying an output c_(j)representing a jth digit of the result from computing the expression ±a₀±a₁.

Also in any case, between the previously mentioned lines, the jth deviceincludes a plurality of switches 24 connected for directing the forwardinput F_(in) to the output c_(j) such that the output is according toone of the formulas: ##EQU7## the plurality of switches 24 also fordirecting a bit value to the forward output F_(out), according toanother of said formulas:

    F.sub.out =(1-p.sub.k)(s.sub.k ⊕x.sub.k)(w.sub.kj ⊕y.sub.k)⊕a.sub.kj ⊕t

    if

    p.sub.0 (s.sub.0 ⊕x.sub.0)⊕(1-p.sub.0)(s.sub.0 ⊕x.sub.0)(w.sub.0j ⊕y.sub.0)⊕a.sub.0j =p.sub.1 (s.sub.1 ⊕x.sub.1)⊕(1-p.sub.1)(s.sub.1 ⊕x.sub.1)(w.sub.1j ⊕y.sub.1)⊕a.sub.1j.

By inserting different values of p₀, p₁, x₀, y₀, k, and t into theforegoing formulas, the formulas can be simplified to specify theswitching required to implement a physical realization of the invention.

Note that this configuration of the invention processes bits as 0's and1's. It would be completely equivalent to replace the 0's and 1's withthe opposite digital value, and this alternative configuration is withinthe scope of the present invention.

Optionally (but illustrated in FIG. 1), the adder-subtractor 2 can havesaid plurality of switches 24 directing the forward input F_(in) to theforward output F_(out) if there is the following inequality:

    p.sub.0 (s.sub.0 ⊕x.sub.0)⊕(1-p.sub.0)(s.sub.0 ⊕x.sub.0)(w.sub.0j ⊕y.sub.0)⊕a.sub.0j ≠p.sub.1 (s.sub.1 ⊕x.sub.1)⊕(1-p.sub.1)(s.sub.1 ⊕x.sub.1)(w.sub.1j ⊕y.sub.1)⊕a.sub.1j.

(This feature is optional because more complicated circuits can bedesigned to skip the middle circuit blocks illustrated in FIG. 11 andFIG. 13.)

In making an adder-subractor according to the present invention, a widerange of switching configurations can be used, though for speed, it ispreferable to select switching that permits an addition-subtractionoperation to be conducted with one clock cycle. Switches can be set onthe leading edge of a clock cycle, and signal representing theaddition-subtraction values can be sent through the set switches on thetrailing edge of the clock cycle. Accordingly, a result c for theinteger expression c=±a₀ ±a₁ can be computed in one clock cycle.

With regard to the plurality of switches 4, consider the various kindsof switches that are separately known in the art. The basic propertiesof two kinds of switches (a OON switch and a 1ON switch) can begeneralized as illustrated in FIG. 2 with a βON switch. β is a parameterwith one of two values (β=0 or 1) that identify one of the two kinds ofswitches discussed below. For either kind of switch, there is an input(incoming signal) and a second input (incoming signal), and an output(outgoing signal). The second input can be designated as a controlvariable z, which is a binary (two-valued) control variable because itcontrols the ON/OFF setting of the switch. The values of the controlvariable z can be z=0 or 1, as illustrated in FIG. 2.

The output of a βON switch is 1 if, and only if, the input is 1 and acontrol variable z (which regulates the setting of the βON switch)equals β. As mentioned, FIG. 2 generalizes the two kinds of switchesbecause regardless of whether β=0 or 1, the output=1 if the input=1 andif z=β; otherwise, the output=0. The properties of βON in FIG. 2 canalso be stated as follows: if z=β the output=input, and if z≠β thenoutput=0; if the control variable z=β then switch βON is ON; if z≠β thenswitch βON if OFF.

FIG. 3 is an illustration of 0ON and 1ON switches. That is, with β=0 or1 (from FIG. 2), the two kinds of switches can be represented as βON and(NOTβ)ON. Each of the two kinds of switches can be used in aconfiguration with the same input, but with different bit values for therespective control variables for each kind of switch. A 0ON switch and a1ON switch are equivalent if the control variables have differentvalues, as shown in FIG. 3. In some cases, it is better to use one orthe other, for example, in a particular application where it is easierto handle the opposite value of the control variable.

With further regard to FIG. 3, the output of a 0ON switch and a 1ONswitch can be described as follows: out₁ =1 if in=1 and z=β, andotherwise out₁ =0; out₂ =1 if in=1 and NOTz=NOTβ, and otherwise out₂ =0.Therefore, out₁ =out₂, which again implies that each kind of switch canreplace the other when control variable z is replaced with NOTz.

FIGS. 4-9 show switches illustrated by graphic symbols: a 0ON switch isrepresented by a graphic symbol () and a 1ON switch is represented byany one of the following graphic symbols \, |, /. FIGS. 4-9 alsoillustrate how 0ON and 1ON switches can be used to make Λ, V, and 0X0switches.

Referring now to FIGS. 4-5, a diagram of a Λ switch is provided. (Theonly difference between FIG. 4 and FIG. 5 is that alternative symbolsare used.) a Λ switch is defined as a switch with a first input (in), asecond input (i.e., a control variable z), and two outputs (out₀ andout₁) such that the first input is directed to one of the two outputsdepending on the value of the control variable z that selects one of thetwo outputs. Said another way, the Λ switch can be characterized asfollows: out_(z) =in, out_(NOTz) =0. Accordingly, for z=0 or 1, out_(z)=in, and out_(NOTz) =0, as illustrated in FIGS. 4-5.

Turning now to FIGS. 6-7, a diagram of a V switch is provided. (Again,the only difference between FIG. 6 and FIG. 7 is that alternativesymbols are used.) A V switch is defined as a switch with two inputs(in₀ and in₁), a third input (i.e., a control variable z), and oneoutput (out) such that one of the two inputs (in₀ or in₁) is selecteddepending on the value of the control variable z, which selects on ofthe two inputs. Accordingly, for z=0 or 1, out=in_(z), as illustrated inFIGS. 6-7.

Regarding FIG. 8 is a diagram of a 0X0 switch. FIG. 9 provides anequivalent switching operation by using a Λ switch. An 0X0 switch isdefined as a switch with two inputs (in₀ and in₁), a third input (i.e.,a control variable z), and two outputs (out₀ and out₁) such that the twoinputs (in₀ and in₁) are each passed straight through or inverteddepending on the value of the control variable z. FIGS. 8-9, for z=0 or1, illustrate the 0X0 and its equivalent, respectively. Another way ofunderstanding a 0X0 switch is with reference to the following: ##EQU8##

In connection with the present invention, any kind of switch can beused, including electric, optic, electromagnetic, mechanical, hydraulic,and/or pneumatic switches. Further, the signals in and out, as well asthe control variables, can be electromagnetic waves (particularlylight), mechanical, and hydraulic and/or pneumatic signals, depending onthe embodiment of the switch preferred. In any of these approaches, theswitch is a "real world" device implementing transformations describedby the above-given formulas.

For speed, it is best to keep the amount of time for switching as smallas possible and to keep the time for passing an incoming signal throughthe switches as short as possible. From this point of view, opticalswitching is preferred, and optical switches are well known. Arepresentative example of an optical switch is discussed in Hyatt M.Gibbs, Optical Bistability: Controlling Light with Light, AcademicPress, Inc. 1985, page 216[5.5]. The optical switch uses one light beamto control whether another light beam passes through the switch. Withsuch a device, the control variable z is a light beam, and if switchingbeam is absent z=0; if switching beam is present z=1.

Another representative example is mentioned in J. Wilson, J. F. B.Hawkes, Optoelectronics, Prentice Hall, Second edition, 1989, page 95.The example involves switching a light beam with applied voltage. Thisexample uses a Pockels cell modulator and a birefrigent material. Alight beam input to the Pockels cell modulator and passed on to thebirefrigent material is switched from a first output position to asecond output position by applying a voltage changed from zero to V_(p)to the birefrigent material. The applied voltage is the controlvariable.

Mechanical, hydraulic, and pneumatic switches are also well known anddescribed in the literature.

First Species: k=p₁ =1, t=x₀ =x₁ =y₀ =y₁ =p₀ =0

Turning now to FIG. 10, a diagram of a species of the device diagramedin FIG. 1 is provided. In FIG. 10 the broken lines delineate two-valuedcontrol variables.

In this particular species, integer parameters for the formulas are asfollows:

    k=p.sub.1 =1, p.sub.0 =t=x.sub.0 =x.sub.1 =y.sub.0 =y.sub.1 =0.

Accordingly, one of the foregoing formulas simplifies, for example, asfollows: ##EQU9##

Additionally, for this species the other of the foregoing formulas canbe simplified, for example, as follows:

    F.sub.out =(1-p.sub.k)(s.sub.k ⊕x.sub.k)(w.sub.kj ⊕y.sub.k)⊕a.sub.kj ⊕t

    if

    p.sub.0 (s.sub.0 ⊕x.sub.0)⊕(1-p.sub.0)(s.sub.0 ⊕x.sub.0)(w.sub.0j ⊕y.sub.0)⊕a.sub.0j =p.sub.1 (s.sub.1 ⊕x.sub.1)⊕(1-p.sub.1)(s.sub.1 ⊕x.sub.1)(w.sub.1j ⊕y.sub.1)⊕a.sub.1j.

    F.sub.out =(1-p.sub.1)(s.sub.1 ⊕x.sub.1)(w.sub.1j ⊕y.sub.1)⊕a.sub.1j ⊕0;

    F.sub.out =a.sub.1j

    if

    s.sub.0 ·w.sub.0j ⊕a.sub.0j =s.sub.1 ⊕a.sub.1j.

Accordingly, for this species the following approach can be implemented:

    F.sub.out =F.sub.in

    if

    p.sub.0 (s.sub.0 ⊕x.sub.0)⊕(1-p.sub.0)(s.sub.0 ⊕x.sub.0)(w.sub.0j ⊕y.sub.0)⊕a.sub.0j ≠p.sub.1 (s.sub.1 ⊕x.sub.1)⊕(1-p.sub.1)(s.sub.1 ⊕x.sub.1)(w.sub.1j ⊕y.sub.1)⊕a.sub.1j ;

    F.sub.out =F.sub.in

    if

    s.sub.0 ·w.sub.0j ⊕a.sub.0j ≠s.sub.1 ⊕a.sub.1j.

FIG. 10 illustrates an embodiment implementing the simplifiedmathematics for this one species of the genus illustrated in FIG. 1.FIG. 10 can be made, for example, with the switches illustrated in FIGS.2-9. Line 26 with an input signal connects to Λ switch 32, and if acontrol variable at switch 32 is zero, the signal on the line 26 ispassed on, as represented in FIG. 10 by arc 26. If the control variableat switch 32 is 1, output from the switch 32 is applied as an input to Λswitch 34. Outputs from the switch 34 are fed as inputs to 0X0 switch36. Outputs from the switch 36 are fed as inputs to 0X0 switch 38. Theoutputs from the switch 38 are fed as inputs to 0X0 switch 40. Oneoutput from switch 40 is fed to line 22, and another output from theswitch 40 is fed to line 26. If a control variable at switch 32 is 0,the output from the switch 32 is passed to the switch 36 (i.e., theswitch 34 is bypassed). In this configuration, if the respective controlvariables are 1, 1, 0, 0, and 0 at the switches 32, 34, 36, 38, and 40,the input signal passes on the line 26. When the respective controlvariables are 0, 0, 0, and 0 at the switches 32, 36, 38, and 40, theinput signal from the line 26 passes to the line 22.

Line 28 connects to Λ switch 42, and if a control variable at the switch42 is 0, a signal on line 28 is passes on, as represented in FIG. 10 byan arc 28. If the control variable at the switch 42 is 1, output fromthe switch 42 is applied as an input to Λ switch 44. Outputs from theswitch 44 are fed as inputs to 0X0 switch 46. Outputs from the switch 46are fed as inputs to 0X0 switch 48. Outputs from the switch 48 are fedas inputs to V switch 50. Output from the switch 50 is split to pass thesignal to the line 22 and to pass the signal on the line 28.

If a control variable at switch 42 is 0, the output from the switch 42is passed to the switch 46 (i.e., the switch 44 is bypassed).

Line 30, which conducts a value of 1, connects to Λ switch 52. If acontrol variable at the switch 52 is 0, the value of 1 on the line 30 ispassed on, as represented in FIG. 10 by an arc, and is split to providean input to V switch 56 and an input to V switch 64. If the value of acontrol variable at the switch 52 is 1, the output from switch 52 isapplied as an input to Λ switch 54. Two outputs from the switch 54 areeach split so that both are fed as inputs to the switch 56 and as inputsto the V switch 64. Output from the switch 56 is applied as an input toΛ switch 58. Outputs from the switch 58 are fed as inputs to a V switch60. If respective control variables at switches 52 and 56 are 0 and 1, avalue of 1 is input to the switch 58. If respective control variablesare 1, 1, and 0 at switches 52, 54, and 56, respectively, a value 1 isinput to the switch 58. Further, if the control variable for the switch58 is different from the control variable for the switch 60, the outputfrom the switch 56 is passed on to the line 26.

Output from the switch 64 is input to a Λ switch 66. If respectivecontrol variables are 0 and 0 at the switches 52 and 64, a value of 1 isinput to the switch 66. If respective control variables are 1, 1, and 1at the switches 52, 54, and 64, and a value of 1 is input to the switch66. Two outputs from the switch 66 are fed as inputs to V switch 68.Output from the switch 64 is passed on to line 28 if the controlvariable for switch 66 is equal to the control variable for the switch68.

Line 70 in FIG. 10 (which is also shown in FIG. 11) can connect to 0ONswitch 62, which is optional, depending on the embodiment. That is, ifthe line 70 inputs a 0 value, output from the circuit in FIG. 10 on theline 70 will be the value input on line 8, etc. However, if the circuitis an optical embodiment, two 1 values input on both lines 8 and 70could cause interference, such that the use of switch 62 would be abetter embodiment. Alternatively, the switch 62 can be located on theline 8. In any case, the line 8 carries a signal representing the valueof a_(0j), and the line 70 carries a signal representing the maximalvalue of all a_(0j) 's from previous positions the same value as thatcarried on line 14 or 16, depending on the value of the parameters x₀and y₀. As shown in FIG. 10, the control variable signals for theswitches 34 and 44, as well as switch 54, are tapped from the line 70.

The switches 52, 32, and 42 are controlled by the control variablesignals on the line 6 as the value for s₀.

The switches 62, 56, 36, 46, and 64 are controlled by the signals a_(0j)tapped from line 8.

The switches 58, 38, 48, and 66 are controlled by the signals input onthe line 10 as the value for s₁.

The switches 60, 40, 50, and 68 are controlled by the signals input onthe line 12 as the value for a_(1j).

The jth device 4 circuit block in FIG. 10 can be incorporated into thecircuit diagram as illustrated in FIG. 11. Additionally, there is a Λswitch 72, which directs a value 1 on the line 30 to either the line 28or the line 26, such that if the value of s₁ on line 10 is 0, then thevalue of 1 is directed to the line 28 in the sequentially first circuitblock of FIG. 10. But if the value of s₁ is 1, then the value of 1 isdirected to the line 26 in the first circuit block of FIG. 10, asillustrated in FIG. 11.

Further, optionally, there is a value of 0 on the line 70 supplied as anoptional input in the first circuit block of FIG. 10 if in a particularembodiment it is necessary to precisely define a₀₀ =0.

FIG. 11 also shows a representative plurality of switches forcontrolling, for output ^(C) s₀ s₁ =(c_(q+2))(c_(q+1) c_(q) . . . c₁that is outside or inside the range of the last group of circuit blocks11 that perform an adder-subtractor computation. There is a 0ON switch73, which is controlled by a control variable c_(q+1), and a 0ON switch74, which is controlled by a control variable c_(q). This is, outputc_(q) is an input to a switch 73, output c_(q+1) is an input to a switch74. Output from switch 74 is fed into a Λ switch 76, which is controlledby a control variable c_(q+2). Output from the switch 73 passes throughto line 78. If c_(q+2) has a value of 1, then output from the switch 76is directed to line 80. If c_(q+2) has a value of 0, then output fromthe switch 76 is directed to the line 78. Accordingly, if the value onthe line 78 is 1, then the number c is over the range, i.e., there is"overflow." If the value on line 80 is 1, then the number c is under therange, i.e., there is "underflow." If the values are 0 on both the lines80 and 78, then the result is in the range, i.e., there is no "overflow"or "underflow." (See Example 6.)

In FIG. 11, depending on the values of the control variables s₀, s₁,a_(0j), a_(1j), and w_(0j) the switches form different paths or end thepaths for these incoming signals. FIG. 11 shows an order of transferredbits.

Second Embodiment of the First Species

Another embodiment of the same species (i.e., the parameters k=p₁ =1, p₀=t=x₀ =x₁ =y₀ =y₁ =0 is illustrated in FIG. 12 (a block) and FIG. 13(which uses the FIG. 12 block). Turning first to FIG. 12, there arethick and thin lines shown: compare thin line 82 with thick line 84;compare thin line 104 with thick line 106. The thin lines representconducting a "thin" bit and the thick lines represent conducting a"thick" bit. In FIG. 12, the lines 82 and 84 carry bits each with avalue of 1. On the lines 104 or 106, at switch 112 a bit value of 1 iscarried. The thick/thin distinction is used to illustrate how in someembodiments, bits can be conducted in the same media but with differentphysical characteristics of the media, such as different polarization,different color of light, or plus/minus voltage. Even the same line canbe used to convey the different characteristics of the media.

The lines 82 and 84 are inputs (so that the bit signals combine in amix) at a Λ switch 86. If a control variable signal s₀ on the line 6 hasa value of 0, the bit signals on lines 82 and 84 are passed on (viaoptional line 88) to an 0X0 switch 92. Thus, if the control variablesignal s₀ on the line 6 is 0 and a_(0j) on the line 8 has a value of 0,then the mix is supplied to line 94 in a way that only the thick bit isconveyed, e.g., by filtering out the thin bit signal. But when s₀ on theline 6 has a value of 1, the mix is input to Λ switch 90. Outputs fromthe switch 90 are inputs to the switch 92 in a manner that if s₀ on line6 has a value of 1, the control variable on the line 70 has a value of1, and the control variable on the line 8 has a value of 0, then the mixis supplied to line 96. Line 96 conveys only a thin bit, e.g., again bymeans of a filter or the like to remove the thick bit.

Λ switch 98 is therefore supplied with either the thin or the thick linebit signals. Outputs of switch 98 are input to 0X0 switch 100 such thatif the control variable s₁ on the line 10 has a value of 1, and controlvariable a_(1j) on the line 12 has a value of 0, a signal is supplied toline 104a, which conveys only a thin bit (again via filtering).Alternatively, if the control variable s₁ on the line 10 has a value of0, and the control variable a_(1j) on the line 12 has a value of 0, thena signal is supplied to line 106a, which conveys only a thick bit (e.g.,again via filtering).

The line 104a connects to the line 104 so that the signal supplied tothe line 104 can be passed on to a next block, etc., as illustrated inFIG. 13. Similarly, line 106a is connected to line 106, etc.

In FIG. 13, if the control variable s₁ =1 at 1ON switch 108 then thinline 104 conducts thin bit 1, and thin bit 1 is fed to Λ switch 112, inthe sequentially first circuit block of FIG. 12 used in FIG. 13. When acontrol variable s₁ =0 at 0ON switch 110 then thick line 106 conductsthick bit 1, and thick bit 1 is also an input to the Λ switch 112 in thefirst circuit block of FIG. 12 used in FIG. 13.

In FIG. 12, if the control variable s₀ =0 at the switch 112, then bit 1(either a thin or thick bit 1) passes on line 114 as an input to an 0X0switch 118. (Line 114 is optional because output from the switch 112 canbe passed directly to the switch 118 in some embodiments, as discussedwith reference to the line 26 and the line 28 in FIG. 10.) If thecontrol variable s₀ =1 at the 112, both the thin and the thick bits,each having a value of 1, are input to Λ switch 116.

Outputs from the switch 116 are fed as inputs to an 0X0 switch 118.Outputs from the switch 118 are fed as inputs to an 0X0 switch 120.Outputs from the switch 120 are fed as inputs to an 0X0 switch 122. A"first" output signal from the switch 122 is split into two portions,with one portion passing to thin line 104 (e.g., via a filter) and another portion passing to thick line 106 (e.g., via a filter). From theline 106 there is a connection to pass output to the line 22; when theline 106 carries a thick bit value of 1 to the line 22, then the digitc_(j) =1. A "second" output signal from the switch 122 passes to thethin line 124 (again, via a filter, for example) which is connected tothe line 22; when the line 124 carries a thin bit value of 1 to the line22, then the digit c_(j) =1. But if the line 124 does not carry the thinbit value of 1 and also the line 106 does not carry the thick bit valueof 1, then the digit c_(j) =0.

In this embodiment, if the respective control variables are 0, 0, 0, and0 at the switches 112, 118, 120, and 122, the input bit 1 to the switch112 passes to the line 124. If the respective control variables are 1,1, 0, 0, and 0 for the switches 112, 116, 118, 120, and 122, the inputto the switch 112 passes to the lines 104 and 106. The lines 104 and 106can be joined if design requirements for a particular embodiment make itpreferable or necessary to pass output on one line.

The line 70 is as described above with regard to FIG. 10. The switches86 and 112 are controlled by the control variable signals on the line 6as the value for s₀. The switches 90 and 116 are controlled by thecontrol variable signal on the line 70. The switches 126, 92, and 118are controlled by the control variable on the line 8 as the value fora_(0j). The switches 98 and 120 are controlled by the control variableon the line 10 as the value for s₁. The switches 100 and 122 arecontrolled by the control variable on the line 12 as the value fora_(1j). In FIG. 12, certain switches can transfer both thick and thinkinds of bits having values of 1. FIGS. 12 and 13 show the order oftransferring bits.

FIG. 12 is similar in many ways to FIG. 10. However, rather than usingthe FIG. 10 approach of than having one input on the line 30 carrying a1 value, in FIG. 12 there is an input on the line 82 and an input online 84, each of these inputs carrying a 1 value. Similarly, rather thanusing the FIG. 11 approach of using one switch 72, in FIG. 13 there arethe two switches 108 and 110. FIG. 13 and FIG. 11 have analogous meansfor determining underflow and overflow.

Of course it is equally possible to make the other embodiments of this(and other) species of the invention, as well as equivalents, asillustrated below.

Third Embodiment of the First Species

For the input integers a₀ and a₁ which have following binaryrepresentations: ##EQU10## for determining the result c=±a₀ ±a₁, a thirdembodiment involves defining a bit sequence c=(c_(q+2))c_(q+1) c_(q) . .. c₁, with c_(q+2) as an output sign bit, as described below. Treat s=s₁for simplicity; recall that s₁ =0 or 1.

"Zero" and "one" are represented by two row columns as shown in Example7.

EXAMPLE 7 ##EQU11##

To avoid use of a NOT operator, which slows down computation, bit 1 islocated in the first or second row exclusively, as shown in Example 6.Bit 0 is therefore also in first or second row, as is also shown inExample 7.

Extend to the left the number a₀ by repeating the a_(0q) bit two timesas follows:

    a.sub.0q+2 =a.sub.0q+1 =a.sub.0q.

Similarly, extend the number a₁ by repeating the a_(1q) bit two times asfollows:

    a.sub.1q+2 =a.sub.1q+1 =a.sub.1q.

A comparison of the respective digits can be conceptually understoodfrom Example 8, in which the first row is denoted as the 0₋₋ row and thesecond row is denoted as the 1₋₋ row.

EXAMPLE 8

    ______________________________________                                        1       1       1     011000   0    1   0.sub.-- row                          0       0       0     100111   1    0   1.sub.-- row                          a.sub.1q+2                                                                            a.sub.1q+1                                                                            a.sub.1q                                                                            . . .    a.sub.11                                                                           0                                         ______________________________________                                    

On the top row of Example 7, in columns q+2, . . . , 0 put the digitsa_(0q+2) a_(0q+1) a_(0q) . . . a₀₁ and s (s=s₁ is put in the 0₋₋column). Below, in the second row, put such bits which satisfy a rulethat a 1 appears only once in each column. In the third row in Example8, in columns q+2, . . . , 0 put bits a_(1q+2) a_(1q+1) a_(1q) . . . a₁₁0.

In Example 8, in the first row in columns q+2, . . . , 1 find the firstdigit from the right that is 1 (where there is no 1, then a₀ is 0). Thatis, if for some position p'(p'≧1) the digit a_(0p') =1, and there is noprevious position r'(p'-1>r'≧1) that a_(0r') =1, then there are twocases. In the first case, if there is a plus sign at a₀ (that is, theexpression is c=+a₀ ±a₁), no bit changes are made in the first andsecond row for bit positions q+2, . . . p'+1. In the second case, ifthere is a minus sign at a₀ (that is, the expression is c=-a₀ ±a₁),exchange (flip) bits from the first and second row for bit positionsq+2, . . . , p'+1. In other words, if at a₀ there is a plus sign (i.e.,s₀ =0), there is no exchange of bits; if at a₀ there is a minus sign(i.e., s₀ =1), there is one exchange or flip of the bits from the firstrow to the second row.

For a bit position j (j=q+2, . . . , 1) along a row, let bit position i(j>i) be the closest column right of j where the bit from that i₋₋column, s₋₋ row equals to a_(1i). (Recall that s=s₁ =0 or 1.) Thus, ifj=1 then i=0.

To find the result c=±a₀ ±a₁, for every bit in the sequencec=(c_(q+2))c_(q+1) c_(q) . . . c₁, with each bit position j (j=q+2, . .. 1), the plurality of switches 24 can implement the following:##EQU12## Fourth Embodiment of the First Species

For the input integers a₀ and a₁ which have following binaryrepresentations: ##EQU13## for determining the result ^(C) s₀ s₁ =±a₀±a₁, a fourth embodiment involves determining the integer c=±a₀ ±a₁=±(a_(0q))a_(0q) a_(0q) a_(0q-1) . . . a₀₁ ±(a_(1q))a_(1q) a_(1q)a_(1q-1) . . . a₁₁ =(c_(q+2))c_(q+1) c_(q) c_(q-1) . . . c₁.

Each of two possible cases are illustrated in Example 9 and Example 10,respectively, wherein the following symbols are used: A=NOTa, S=NOTs. Ifs₀ =0 or if a₀ =0, then the first row is denoted as 0₋₋ row and thesecond row is denoted as 1₋₋ row, with s=s₁. This is the same case asc=a₀ ±a₁.

EXAMPLE 9

    ______________________________________                                        column                                                                        q+2  q+1    q      q-1   . . .                                                                              p'   . . .                                                                              1    0                                ______________________________________                                        a.sub.0q                                                                           a.sub.0q                                                                             a.sub.01                                                                             a.sub.0q-1                                                                          . . .                                                                              a.sub.0p'                                                                          . . .                                                                              a.sub.01                                                                           s   0.sub.-- row                 A.sub.0q                                                                           A.sub.0q                                                                             A.sub.0q                                                                             A.sub.0q-1                                                                          . . .                                                                              A.sub.0p'                                                                          . . .                                                                              A.sub.01                                                                           S   1.sub.-- row                 a.sub.1q                                                                           a.sub.1q                                                                             a.sub.1q                                                                             a.sub.1q-1                                                                          . . .                                                                              a.sub.1p'                                                                          . . .                                                                              a.sub.11                                                                           0                                ______________________________________                                    

In the second case illustrated is in Example 10: if s₀ =1 (which is thesame as c=-a₀ ±a₁), for some position p' (p'≧1) bit a_(p') =1, there isno position r' (p'-1>r'≧1) that bit a_(r') =1. Then in the first row,columns p', . . . , 0 are labeled as 0₋₋ row, columns q+2, . . . , p'+1are labeled as 1₋₋ row; exchange (flip) the labels such that in thesecond row columns p', . . . , 0 are labeled as 1₋₋ row, and columnsq+2, . . . , p'+1 are labeled as 0₋₋ row.

EXAMPLE 10

    __________________________________________________________________________    column                                                                        q+2    . . .                                                                             p'+1   p' p'-1                                                                              . . .                                                                            1  0                                              __________________________________________________________________________    1.sub.-- row                                                                      a.sub.0q                                                                         . . .                                                                             a.sub.0p'+1                                                                       |                                                                       1  0   . . .                                                                            0  s 0.sub.-- row                                 0.sub.-- row                                                                      A.sub.0q                                                                         . . .                                                                             A.sub.0p'+1                                                                       |                                                                       0  1   . . .                                                                            1  S 1.sub.-- row                                     a.sub.1q                                                                         . . .                                                                             a.sub.1p'+1                                                                          a.sub.1p'                                                                        a.sub.1p'-1                                                                       . . .                                                                            a.sub.11                                                                         0                                              __________________________________________________________________________

In either of the previously-discussed two cases, to find the resultc=±a₀ ±a₁, for every bit in the sequence c=(c_(q+2))c_(q+1) c_(q) . . .c₁, with each bit position j (j=q+2, . . . , 1), c_(j) is as follows:For j (j=q+2, . . . , 1) let bit position i (j>i≧0) be the closest tothe right of j where i₋₋ column, s₋₋ row bit equals to a_(1i). Theplurality of switches 24 can implement switching such that c_(j) is asfollows: ##EQU14## Fifth Embodiment of the First Species

Another embodiment of the first species of the present invention can bemade to minimize the use of the NOT operation. Again, for input integersa₀ and a₁ having the following binary representations: ##EQU15## outputis again defined as c=^(C) s₀ s₁ =±a₀ ±a₁, c=(c_(q+2))c_(q+1) c_(q) . .. c₁, where c_(q+2) is a sign bit. Again, assuming that a_(0q+2)=a_(0q+1) =a_(0q) and a_(1q+2) =a_(1q+1) =a_(1q) ; treating s=s₁simplicity; and recalling that s₁ =0 or 1, the following approach can beused.

Form a temporary second row of one's (the bits 1) at positions q+2, . .. , 0 labeled with 1₋₋ row. Next, make a first 0₋₋ row (above thetemporary second row) by shifting up bit 1 to the same positions asfollows: if s=1 from the rightmost 0₋₋ position of the 1₋₋ row, shift upbit 1 to the 0₋₋ row; if p'≧1 is the smallest index that a_(p') =1, thenfrom the position p' of the 1₋₋ row shift up bit 1 and from everyposition r'(q+2≧r'≧p'+1) of the 1₋₋ row if a_(r') ≠s₀ shift up bit 1.

In the event that s=0, put bit 1 over the rows at every positionk'(q+2≧k'≧1) if b_(k') =1, and label this sequence of one's with b₋₋row; in the event that s=1, put a bit 1 below the rows at every positionk'(q+2≧k'≧1) if b_(k') =1, and label this sequence of one's with b₋₋row, the third row. In the fourth row, there is a result c₋₋ row atevery position n(q+2≧n≧1) there is bit 1 if c_(n) =1.

In every i₋₋ column (q+2≧i≧0) if at both s₋₋ row and b₋₋ row eitherthere are bits 1 or there is no bit 1 then in this i₋₋ column mark{darken} bit 1 which is in 0₋₋ row or 1₋₋ row.

The foregoing approach holds for one of the following two cases:

1) If a marked bit 1 is in the 0₋₋ row then in the result c₋₋ row bit 1is in the next marked column (if exist), or

2) If a marked bit 1 is in the 1₋₋ row then in the result c₋₋ row bit 1there is in the next {not marked} and every consecutive not markedcolumn (if any exist).

In the result c₋₋ row remaining positions are zero's. As with theabove-discussed species, this species is made by using the plurality ofswitches 24 to implement these cases.

Sixth Embodiment of the First Species

Once more, assume that the input integers a₀ and a₁ have followingbinary representations: ##EQU16## Output integer c=^(C) s₀ s₁ =±a₀ ±a₁,c=(c_(q+2))c_(q+1) c_(q) . . . c₁. Assume: a_(0q+2) =a_(0q+1) =a_(0q),a_(1q+2) =a_(1q+1) =a_(1q), a₀₀ =s₁ and a₁₀ =0. Put the digits a_(0q+2)a_(0q+1) a_(0q) . . . a₀₁ a₀₀ on the top row, below put row of digitsa_(1q+2) a_(1q+1) a_(1q) . . . a₁₁ a₁₀.

Assume for a moment that parameter p'=q+2 and index i₀ =0, but if s₀ =1and t'≧1 is a minimal index such that a_(0t') =1 then let p'=t'. For aniterate index j=0, 1, 2, . . . find a minimal position i_(j+1)(p'≧i_(j+1) >i_(j) ≧0) where the following equalities hold:

    .sup.a 0i.sub.j+1 =NOT.sup.a 0i.sub.j

    and

    .sup.a 1i.sub.j+1 =NOT.sup.a 1i.sub.j.

If s₀ =1 and M≧0 is a maximal index such that i_(M) ≦p' (p'≧i_(M)) thenfix a position i_(M+1) (i_(M+1) >p') that ^(a) 0i_(M+1) =^(a) 0i_(M) and^(a) 1i_(M+1) =NOT^(a) 1i_(M) ; for an iterate index r'=0, 1, 2, . . .find a minimal position i_(M+1+r'+1) (q≧i_(M+1+r'+1) >i_(M+1+r')) wherethe following equalities hold:

    .sup.a 0i.sub.M+1+r'+1 =NOT.sup.a 0i.sub.M+1+r'

    and

    .sup.a 1i.sub.M+1+r'+1 =NOT.sup.a 1i.sub.M+1+r'.

Columns 1 to q+2 can be separated into groups of consecutive columns. Afirst step of separation forms groups of columns between i_(j) and i_(j)+1 (iterate j≧1, j≠M if s₀ =1 and i_(M) =p'). Then there can be a second(i.e., conditional) step of separation to form additional groups ofcolumns between p' and p'+1 if s₀ =1 and p'>i_(M).

In each odd class (1st, 3rd, . . . ) of j columns a digit c_(j) =1 ifa_(0j) ≠a_(1j) ; in each even class (2nd, 4th, . . . ) of j columns adigit c_(j) =1 if a_(0j) =a_(1j). All other bit positions have zero's.In using the present invention consider the following four examples forthe sixth embodiment of the first species.

As a first example, consider a₀ =0, a₁ =(1)010100. The objective is tofind a binary result for c=a₀ -a₁. The solution is as follows: s₀ =0, s₁=1, q=7, p'=9, i₀ =0, i₁ =3. A numeric illustration is shown below inExample 10.

EXAMPLE 10 ##STR1##

As a second example, consider a₀ =(1)0111000101, a₁ =(0)11110010. Theobjective is to find a binary result of c=a₀ +a₁. The solution is asfollows: s₀ =s₁ =0, q=11, p'=13, i₁ =7, i₂ =9. A numeric illustration isshown in Example 11.

EXAMPLE 11 ##STR2## Now for a third example, consider a₀ =(1)0100100, a₁=(0)1111010. The objective is to find binary c=-a₀ +a₁. The solution isa follows: s₀ =1, s₁ =0, q=8, p'=3, M=0, (p'>i_(M) =0), i₁ =4, i₂ =8. Anumeric illustration is provided in Example 12. EXAMPLE 12 ##STR3##

Finally, as a fourth example, consider a₀ =(0)101101000, a₁=(1)01010001. Again, the objective is to find binary c=-a₀ -a₁. Thesolution is as follows: s₀ =s₁ =1, p'=4, i₁ =1, i₂ =4, M=2, (p'=i_(M))i₃ =7, i₄ =8, i₅ =9. A numeric illustration is provided in Example 13.

EXAMPLE 13 ##STR4## Second Species, First Embodiment: t=x₀ =x₁ =y₀ =y₁=k=p₀ =0, p₁ =1

For the general case of an adder-subtractor device for computing aresult c for an expression c=±a₀ ±a₁, the functioning of theadder-subtractor of the present invention can be better understood, andequivalent circuits can better be recognized, by focussing on thefollowing ways to obtain c_(j) on the line 22.

Again, two input integers a₀ and a₁ have following binaryrepresentations: ##EQU17## Let ^(c) s₀ s₁ =±a₀ ±a₁.

The integers a₀ and a₁ can be placed into their extended forms toposition q+2 {i.e., the two's complement in (q+2)₋₋ bits}:

    a.sub.0 =(a.sub.0q+2)a.sub.0q+1 a.sub.0q . . . a.sub.01,

    a.sub.1 =(a.sub.1q+2)a.sub.1q+1 a.sub.1q . . . a.sub.11,

where extended bits satisfy equalities: a_(0q+2) =a_(0q+1) =a_(0q) anda_(1q+2) =a_(1q+1) =a_(1q). For additional bits, let digits a₀₀ =a₁₀ =0.

The parameters s₀ and s₁ uniquely defined in the expression ^(c) s₀ s₁=±a₀ ±a₁ by the signs at the integers. Let m be a bit position(q+2≧m≧1), k=0 or 1; for integer a_(k) and position m define parameterw_(km) as follows: w_(km) =1 if there is a position p' (m-1≧p'≧1) suchthat a_(kp') =1; otherwise, w_(km) =0. In other words, w_(km) equals toa maximal digit a_(kk') from previous positions k' (k>k'≧0).

Accordingly, as illustrated in FIG. 12 and 13, the line 70 conveys thesignal w_(kj) for use in the plurality of switches 24 to compute theformulas: ##EQU18## The plurality of switches 24 directs the forwardinput F_(in) to the forward output F_(out) if

    p.sub.0 (s.sub.0 ⊕x.sub.0)⊕(1-p.sub.0)(s.sub.0 ⊕x.sub.0)(w.sub.0j ⊕y.sub.0)⊕a.sub.0j ≠p.sub.1 (s.sub.1 ⊕x.sub.1)⊕(1-p.sub.1)(s.sub.1 ⊕x.sub.1)(w.sub.1j ⊕y.sub.1)⊕a.sub.1j.

Assuming in above formulas that p₀ =x₀ =x₁ =y₀ =y₁ =t=0, p₁ =1 we get:

    F.sub.out =(1-p.sub.k)s.sub.k ·w.sub.kj ⊕a.sub.kj if s.sub.0 ·w.sub.0j ⊕a.sub.0j =s.sub.1 ⊕a.sub.1j ;

    c.sub.j =s.sub.0 ·w.sub.0j ⊕a.sub.0j ⊕a.sub.1j ⊕(1-s.sub.k ·p.sub.k)s.sub.1-k ·p.sub.1-k ⊕F.sub.in

The plurality of switches 24 directs the forward input F_(in) to theforward output F_(out) if s₀ ·w_(0j) ⊕a_(0j) ≠s₁ ⊕a_(1j).

Thus, FIGS. 12 and 13 illustrate k=0. However, if k=1, similar circuitscan be defined as follows: replace a_(0j) with a_(1j) and replace s₀with s₁.

In a general case, fine (and mark or memorize) all r positions for(q+2≧r≧0) where s₀ ·w_(0j) ⊕a_(0j) =s₁ ⊕a_(1j) ; for any such r positionidentify a corresponding emit position. From emit r position send(emitted) is a bit F_(out) named emit bit (ebit).

Any ebit value can be represented with any one of two different statesof matter or energy, e.g., positive or negative voltage or magneticpolarity, light present or absent, etc.). Ebits are emitted from allemit positions; every ebit arrives at successive not marked positions upto the next marked position included in the computation (if such aposition exists). The ebit induces one of the two different states. Anebit reaching a marked position induces the same ebit value state, butif the ebit reaches a not-marked position, a NOTebit (1-ebit, otherstate) state is induced. Thus, at position j (q+2≧j≧1) a state's valueinduced by an arrived ebit equals c_(j).

Second Species, Second Embodiment: t=x₀ =x₁ =y₀ =y₁ =k=p₀ =0, p₁ =1

The adder-subtractor device can also be mad by using p₀ ·p₁ =t=0 andk=p₀, such that the plurality of switches, between the lines, fordirecting to the forward output F_(out) the bit value, directs accordingto a simplified version of the one of said formulas, provided that ifj=1 then F_(in) =p_(1-k) ·s_(1-k) :

    F.sub.out =(1-p.sub.k)(s.sub.k ⊕x.sub.k)(w.sub.kj ⊕y.sub.k)⊕a.sub.kj if

    p.sub.0 (s.sub.0 ⊕x.sub.0)⊕(1-p.sub.0)(s.sub.0 ⊕x.sub.0)(w.sub.0j ⊕y.sub.0)⊕a.sub.0j =p.sub.1 (s.sub.1 ⊕x.sub.1)⊕(1-p.sub.1)(s.sub.1 ⊕x.sub.1)(w.sub.1j ⊕y.sub.1)⊕a.sub.1j and

    F.sub.out =F.sub.in

otherwise; and

the plurality of switches, also for directing the forward input F_(in)to the output c_(j) such that the output is according to the other ofsaid formulas directs according to a simplified version of the other ofsaid formulas:

    c.sub.j =F.sub.in if p.sub.0 (s.sub.0 ⊕x.sub.0)⊕(1-p.sub.0)(s.sub.0 ⊕x.sub.0)(w.sub.0j ⊕y.sub.0)⊕a.sub.0j =p.sub.1 (s.sub.1 ⊕x.sub.1)⊕(1-p.sub.1)(s.sub.1 ⊕x.sub.1)(w.sub.1j ⊕y.sub.1)⊕a.sub.1j and c.sub.j =1-F.sub.in

otherwise. In this situation, the formulii simplified by inserting theabove-given integer values has been simplified to an equivalent by usingmathematical identities.

Third Species: p₀ =p₁ =1; t=x₀ =x₁ =y₀ =y₁ =0

An adder-subtractor device for computing a result c for an expressionc=±a₀ ±a₁ with the above-mentioned formulas: ##EQU19## and the pluralityof switches directs the forward input F_(in) to the forward outputF_(out) if

    p.sub.0 (s.sub.0 ⊕x.sub.0)⊕(1-p.sub.0)(s.sub.0 ⊕x.sub.0)(w.sub.0j ⊕y.sub.0)⊕a.sub.0j ≠p.sub.1 (s.sub.1 ⊕x.sub.1)⊕(1-p.sub.1)(s.sub.1 ⊕x.sub.1)(w.sub.1j ⊕y.sub.1)⊕a.sub.1j.

The integer parameters inserted into the foregoing can be formulas topermit simplification as follows: ##EQU20## and the plurality ofswitches directs the forward input F_(in) to the forward output F_(out)if

    1(s.sub.0)⊕(0)(s.sub.0)(w.sub.0j)⊕a.sub.0j ≠1(s.sub.1)⊕(0)s.sub.1)(w.sub.1j)⊕a.sub.1j.

In above formulas assume first that k=0,

F_(out) =a_(0j) if s₀ ⊕a_(0j) =s₁ ⊕a_(1j).

c_(j) =a_(0j) ⊕a_(1j) ⊕(1-s₀)s₁ ⊕F_(in) ⊕s₀ ·s₁·((w_(0j))⊕(w_(1j))⊕(w_(0j))(w_(1j))).

the plurality of switches directs the forward input F_(in) to theforward output F_(out) if s₀ ⊕a_(0j) ≠s₁ ⊕a_(1j).

or that k=1,

F_(out) =a_(1j) if s₀ ⊕a_(0j) =s₁ ⊕a_(1j).

c_(j) =a_(0j) ⊕a_(1j) ⊕(1-s₁)s₀ ⊕F_(in) ⊕s₀ ·s₁·((w_(0j))⊕(w_(1j))⊕(w_(0j))(w_(1j))).

the plurality of switches directs the forward input F_(in) to theforward output F_(out) if s₀ ⊕a_(0j) ≠s₁ ⊕a_(1j).

This simplification can now be implemented in switching, i.e., in theplurality of switches 24. More details below.

One embodiment of this species to computing the result reflects thefollowing. The integers a₀ and a₁ can be represented in extended formsto a position q+2 {two's complement in (q+2) bits } as follows:

    a.sub.0 =(a.sub.0q+2)a.sub.0q+1 a.sub.0q . . . a.sub.01,

    a.sub.1 =(a.sub.1q+2)a.sub.1q+1 a.sub.1q . . . a.sub.11,

where extended bits satisfy the following equalities: a_(0q+2) =a_(0q+1)=a_(0q) and a_(1q+2) =a_(1q+1) =a_(1q). For additional bits, let digitsa₀₀ =a₁₀ =0. The parameters s₀ and s₁ are uniquely defined in theexpression ^(c) s₀ s₁ =±a₀ ±a₁. If the signs for the expression ^(c) s₀s₁ are identical, for any bit position j between (q+2≧j≧1) let i be themaximal bit position to the right less than the bit position j (j>i)where bits a_(0i) and a_(1i) are identical. Example 14 illustrates thebit locations of j and i where bits a_(0i) and a_(1i) are same.

Example 14 ##EQU21##

Similarly, if the signs for the expression ^(C) s₀ s₁ are different, forany bit position j between (q+2≧j≧1) let i be the maximal bit positionto the right less than the bit position j (j>i) where bits a_(0i) anda_(1i) are different. Example 15 illustrates the bit locations of j andi where bits a_(0i) and a_(1i) are different.

Example 15 ##EQU22##

In Examples 14 and 15, i can be found. But if in other examples i≧1cannot be found, then assume that i=0.

Temporary binary digits c_(j) (q+2≧j≧1) can be obtained as follows.Among the bits a_(0j), a_(1j), a_(s1i) two are identical (example 6);(if s₁ =0 then ^(a) s₁ i=a_(0i), if s₁ =1 then ^(a) s₁ i=a_(1i)). Letc_(j) be equal to the remaining bit. If the product s₀ ·s₁ =0, theinteger ^(C) s₀ s₁ has following q+2 bit representation: ^(C) s₀ s₁=(c_(q+2))c_(q+1) c_(q) . . . c₁ =(c_(q+2))c_(q+1) c_(q) . . . c₁ where(c_(q+2))=(c_(q+2)) is a sign bit.

If s₀ =s₁ =1, the digits c_(j) (q+2≧j≧1) form the opposite number toc₁₁. That is, c₁₁ =-(c(c_(q+2))c_(q+1) c_(q) . . . c₁. Thepreviously-described procedure for obtaining the opposite integers isthen applied: -(c_(q+2))c_(q+1) c_(q) . . . c₁ =(c_(q+2))c_(q+1) c_(q) .. . c₁. The plurality of switches 24 can implement this switching.

Second Embodiment of Third Species

A second embodiment of computing the result reflects the following.Again, the integers a₀ and a₁ can be represented in extended forms to aposition q+2 {two's complement in (q+2) bits} as follows:

    a.sub.0 =(a.sub.0q+2)a.sub.0q+1 a.sub.0q . . . a.sub.01,

    a.sub.1 =(a.sub.1q+2)a.sub.1q+1 a.sub.1q . . . a.sub.11,

where extended bits satisfy the equalities: a_(0q+2) =a_(0q+1) =a_(0q)and a_(1q+2) =a_(1q+1) =a_(1q). For additional bits, let digits a₀₀ =a₁₀=0. The parameters s₀ and s₁ are uniquely defined in the expression ^(C)s₀ s₁ =±a₀ ±a₁. If the signs at the integers a₀ and a₁ are the same (s₀=s₁), mark first integer a₀. If the signs are different, the integerwhich has a + (`plus`) sign is marked and on 0₋₋ position of the markedinteger, change the bit that was assumed to be 0 into 1 (`one`).

Compare the two sins at the integers a₀ and a₁, and compare bits at thesame bit positions; if the signs at the integers are identical for thebit position m=q+2, . . . , 0 mark every position m with identicaldigits. See Example 12.

Example 16 ##EQU23##

The signs at the binary numbers in Example 12 are the same (i.e., bothnegative), and the bits on the 0, 1, 5, 6, and 7 positions are the same,but the bits at the other positions are different.

Similarly, compare the two signs at the integers a₀ and a₁, and comparebits at the same bit positions; if the signs at the integers aredifferent for the bit position m=q+2, . . . , 0 mark every position mwith different digits.

In the marked integer and each of the marked positions there is an ebit;for the marked integer, the position m and the value (0 or 1) of everyebit is defined. From a next position of any ebit up to a next markedposition (or to the (q+2)₋₋ position if there is no next markedposition), if j is a marked position then digit c_(j) =nearby rightebit; if j is a NOTmarked position then digit c_(j) =NOTnearby rightebit.

If the product s₀ ·s₁ =0, the integer ^(C) s₀ s₁ has the following q+2bit representation: ^(C) s₀ s₁ =(c_(q+2))c_(q+1) c_(q) . . . c₁=(c_(q+2))c_(q+1) c_(q) . . . c₁ where (c_(q+2))=(c_(q+2)) is a signbit.

If s₀ =s₁ =1, the digits c₁ (q+2≧j≧1) form an opposite number to c₁₁. Asdescribed above, c₁₁ =-(c_(q+2))c_(q+1) c_(q) . . . c₁, and thepreviously-described procedure for obtaining the opposite integers isthen applied to reach the result.

    -(c.sub.q+2)c.sub.q+1 c.sub.q . . . c.sub.1 =(c.sub.q+2)c.sub.q+1 c.sub.q . . . c.sub.1

As an illustration of the second embodiment of the second species, inExample 17, let an integer a₀ with a sign be on the top row and a₁ witha sign be on the second row. If the signs at the integers are the samein the rightmost 0₋₋ column, put zero's in the rightmost 0₋₋ column foreach and mark either the first or the second integer, for instance thefirst (i.e., in the first row). If the signs are different on the rowwhere there is a `plus` sign in 0₋₋ column put a 1 in 0₋₋ column to markthis as an emit row and put a 0 in 0₋₋ column in the other row.

Example 17 ##EQU24##

If the signs are identical for m=0, . . . , q+2 then mark every columnwith identical digits; in the marked row and marked column there is anebit. If the signs are different for m=0, . . . , q+2 then mark everycolumn with different digits; in the marked row and marked column thereis an ebit.

From a next position of an ebit up to a next emit column, if the nextemit column exists, or otherwise to the (q+2)₋₋ position, if j is amarked position then the digit c_(j) equals the nearby right ebit; if jis not a marked position then the digit c_(j) is different then thenearby right ebit.

In Example 18 below, for the marked row in Example 13, each position andvalue of every ebit is defined and noted between bars as follows:|e_(index) |. On the second row in Example 14 there are bits c_(j)(j=q+2, . . . , 1).

Example 18 ##EQU25##

I claim:
 1. An adder-subtractor device comprising: a jth device for eachbit position j for computing a result c for an expression c=±a₀ ±a₁where a₀ and a₁ are binary numbers, the jth device being from a groupconsisting of devices defined by formulas using integer parameters k,p₀, p₁, t, x₀, x₁, y₀, and y₁, each said parameter having a nonnegativeinteger value that is less than two, the jth device including:a linecarrying an input s₀ representing x₀ when the sign at the a₀ number inthe expression is positive, and representing 1-x₀ when the sign at thea₀ number in the expression is negative; a line carrying an input a_(0j)representing a jth digit of the a₀ number; a line carrying an input s₁representing x₁ when the sign at the a₁ number in the expression ispositive, and representing 1-x₁ when the sign at the a₁ number in theexpression is negative; a line carrying an input a_(1j) representing ajth digit of the a₁ number; the jth device further including a linecarrying an input w_(0j) =1-y₀ when s₀ =1-x₀ and if any previous bitposition of the a₀ number is 1, and w_(0j) =y₀ when s₀ =1-x₀ and thereis no 1 on any previous bit position, and w_(0j) has a nonnegativeinteger value that is less than 2 when s₀ =x₀ ; the jth device furtherincluding a line carrying an input w_(1j) =1-y₁ when s₁ =1-x₁ and if anyprevious bit position of the a₁ number is 1, and w_(1j) =y₁ when s₁=1-x₁ and there is no 1 on any previous bit position, and w_(1j) has anonnegative integer value that is less than 2 when s₁ =x₁ ; at least oneline carrying a forward input F_(in) ; at least one line carrying aforward output F_(out) ; a line carrying an output c_(j) representing ajth digit of the result from computing the expression ±a₀ ±a₁ ; and aplurality of switches, between the lines, for directing to the forwardoutput F_(out) a bit value, according to a first of said formulas:

    F.sub.out =(1-p.sub.k)(s.sub.k ⊕x.sub.k)(w.sub.kj ⊕y.sub.k)⊕a.sub.kj ⊕t only if

    p.sub.0 (s.sub.0 ⊕x.sub.0)⊕(1-p.sub.0)(s.sub.0 ⊕x.sub.0)(w.sub.0j ⊕y.sub.0)⊕a.sub.0j =p.sub.1 (s.sub.1 ⊕x.sub.1)⊕(1-p.sub.1)(s.sub.1 ⊕x.sub.1)(w.sub.1j ⊕y.sub.1)⊕a.sub.1j,

the plurality of switches also for directing the forward input F_(in) tothe output c_(j) such that the output is according to a second of saidformulas: ##EQU26##
 2. The adder-subtractor of claim 1, wherein saidplurality of switches includes switches to direct the forward inputF_(in) to the forward output F_(out) if

    p.sub.0 (s.sub.0 ⊕x.sub.0)⊕(1-p.sub.0)(s.sub.0 ⊕x.sub.0)(w.sub.0j ⊕y.sub.0)⊕a.sub.0j ≠p.sub.1 (s.sub.1 ⊕x.sub.1)⊕(1-p.sub.1)(s.sub.1 ⊕x.sub.1)(w.sub.1j ⊕y.sub.1)⊕a.sub.1j.


3. The adder-subtractor device of claim 2, wherein:the nonnegativeinteger values for the parameters are such that s₀ ⊕x₀ =s₁ +x₁ =0, so asto compute a result c for a simplified version of the expression c=±a₀±a₁, the simplified version being c=a₀ +a₁, such that the plurality ofswitches, between the lines, for directing to the forward output F_(out)the bit value, directs according to a simplified version of the first ofsaid formulas:

    F.sub.out =a.sub.kj if a.sub.0j =a.sub.1j ;

and wherein the plurality of switches also directs according to asimplified version of the second of said formulas:

    c.sub.j =a.sub.0j ⊕a.sub.1j ⊕F.sub.in ;

and wherein the plurality of switches directs the forward input F_(in)to the forward output F_(out) if a_(0j) ≠a_(1j).
 4. The adder-subtractordevice of claim 2, wherein:the nonnegative integer values for theparameters are such that t=s₀ ⊕x₀ =0 and s₁ ⊕x₁ =1, so as to compute aresult c for a simplified version of the expression c=±a₀ ±a₁, thesimplified version being c=a₀ -a₁, such that the plurality of switches,between the lines, for directing to the forward output F_(out) the bitvalue, directs the forward input F_(in) to the forward output F_(out) ifa_(0j) ≠1-a_(1j).
 5. The adder-subtractor device of claim 2, wherein:thenonnegative integer values for the parameters are such that p₀ ·p₁ =t=0and k=p₀, such that the plurality of switches, between the lines, fordirecting to the forward output F_(out) the bit value, directs accordingto a simplified version of the first of said formulas, provided that ifj=1 then F_(in) =p_(1-k) ·s_(1-k) :

    F.sub.out =(1-p.sub.k)(s.sub.k ⊕x.sub.k)(w.sub.kj ⊕y.sub.k)⊕a.sub.kj if

    p.sub.0 (s.sub.0 ⊕x.sub.0)⊕(1-p.sub.0)(s.sub.0 ⊕x.sub.0)(w.sub.0j ⊕y.sub.0)⊕a.sub.0j =p.sub.1 (s.sub.1 ⊕x.sub.1)⊕(1-p.sub.1)(s.sub.1 ⊕x.sub.1)(w.sub.1j ⊕y.sub.1)⊕a.sub.1j and F.sub.out =F.sub.in otherwise;

and the plurality of switches, also for directing the forward inputF_(in) to the output c_(j) according to a simplified version of thesecond of said formulas:

    c.sub.j =F.sub.if if p.sub.0 (s.sub.0 ⊕x.sub.0)⊕(1-p.sub.0)(s.sub.0 ⊕x.sub.0)(w.sub.0j ⊕y.sub.0)⊕a.sub.0j =p.sub.1 (s.sub.1 ⊕x.sub.1)⊕(1-p.sub.1)(s.sub.1 ⊕x.sub.1)(w.sub.1j ⊕y.sub.1)⊕a.sub.1j and c.sub.j =1-F.sub.in otherwise.


6. The adder-subtractor of claim 5, wherein:said line carrying saidforward input conducts a mix of a first bit 1 and a second bit 1 to afirst Λ switch in said plurality of switches for directing, the first Λswitch being controlled by a first control variable signal s₀ such thatif the control variable signal is 0, the first Λ switch passes the bit 1signals on to a first 0X0 switch, the first 0X0 switch being controlledby a third control variable signal a_(0j) such that if the third controlvariable said a_(0j) signal is 0, then the mix is supplied to a meansfor filtering out a first of the bit 1 signals and input a second of thebit 1 signals to a third Λ switch, but if the first control variablesignal s₀ is 1, the mix is input to a second Λ switch, the second Λswitch being controlled by the second control variable w_(0j) such thatoutputs from the second Λ switch are fed as inputs to the first 0X0switch such that when the first control variable signal s₀ is 1 and thesecond control variable w_(0j) is 1 and said line carrying an inputa_(0j) is 0, the mix is supplied to a filter to produce a remainingfirst bit 1 from the mix, such that the third Λ switch being controlledby fourth control variable s₁ is supplied the remaining bit signal fromthe mix so that the outputs of third Λ switch are input to second 0X0switch, the second 0X0 switch being controlled said line carrying theinput a_(1j) such that when s₁ is 1, and when the input a_(1j) is 0, anoutput from the second 0X0 switch is conducted to a filter such thatonly the first bit 1 is passed to a first forward output line, and whens₁ is 0 and when the input a_(1j) is 0, a second output from the second0X0 switch is conducted to a filter and only the second bit 1 is passedon to the second forward output; and further comprising a second linecarrying a second forward input to a fourth Λ switch, the second forwardinput being one from the pair consisting of the first bit 1 and thesecond bit 1, the fourth Λ switch being controlled by the first controlvariable s₀ such that if s₀ =0, then the one bit 1 passes on as an inputto a third 0X0 switch, but if the s₀ =1, the one bit 1 is fed as aninput to the fifth Λ switch, the fifth Λ switch being controlled by thesecond control variable w_(0j) such that outputs are fed as inputs tothe third 0X0 switch, the third 0X0 switch being controlled by the thirdcontrol variable on the line carrying the input a_(0j), such that theoutputs third 0X0 switch are fed as inputs to a fourth 0X0 switch, thefourth 0X0 switch being controlled by the fourth control variable s₁such that outputs from the fourth 0X0 switch are fed as inputs fifth 0X0switch, the fifth 0X0 switch being controlled by the fifth controlvariable a_(1j) such that outputs from the fifth 0X0 switch areconducted to the forward output line and to the line outputting c_(j),and when the control variables s₀ =1, w_(0j) =1, a_(0j) =0, s₁ =0, anda_(1j) =0, output from the fifth 0X0 switch is conducted to a filtersuch that if the first bit 1 is received as the second forward input,the filter passes that first bit 1 to the forward output, and if thesecond bit 1 is received as the second forward input, the filter passesthat second bit 1 to the second forward output line and to the lineoutputting c_(j), but if the control variables s₀ =0, a_(0j) =0, s₁ =0and a_(1j) =0, the filter passes the first bit 1 to the line outputtingc_(j) ; and wherein the line carrying an input w_(0j) conducts to theline carrying an input a_(0j) via a 0ON switch in said plurality ofswitches for directing, said 0ON switch being controlled by one of thecontrol variables from a group consisting of a_(0j) and w_(0j).
 7. Theadder-subtractor of claim 2, wherein j is greater than
 1. 8. Theadder-subtractor of claim 7, wherein,prior to receipt of the F_(in)signal by each said jth device, each said line carrying the forwardinput F_(in) is simultaneously connected by setting a path through theswitches of each said jth device to each said line carrying the outputc_(j).
 9. The adder-subtractor of claim 8, wherein at least one of saidlines carries a mix of bits.
 10. The adder-subtractor of claim 1,wherein j is greater than
 1. 11. The adder-subtractor of claim 10,wherein,prior to receipt of the F_(in) signal by each said jth device,each said line carrying the forward input F_(in) is simultaneouslyconnected by setting a path through the switches of each said jth deviceto each said line carrying the output c_(j).
 12. The adder-subtractor ofclaim 11, wherein at least one of said lines carries a mix of bits. 13.The adder-subtractor device of claim 1, wherein:the nonnegative integervalues for the parameters are such that p₀ ·p₁ =t=0 and k=p₀, such thatthe plurality of switches, between the lines, for directing to theforward output F_(out) the bit value, directs according to a simplifiedversion of the first of said formulas, provided that if j=1 then F_(in)=p_(1-k) ·s_(1-k) :

    F.sub.out =(1-p.sub.k)(s.sub.k ⊕x.sub.k)(w.sub.kj ⊕y.sub.k)⊕a.sub.kj if

    p.sub.0 (s.sub.0 ⊕x.sub.0)⊕(1-p.sub.0)(s.sub.0 ⊕x.sub.0)(w.sub.0j ⊕y.sub.0)⊕a.sub.0j =p.sub.1 (s.sub.1 ⊕x.sub.1)⊕(1-p.sub.1)(s.sub.1 ⊕x.sub.1)(w.sub.1j ⊕y.sub.1)⊕a.sub.1j and F.sub.out =F.sub.in otherwise;

and the plurality of switches, also for directing the forward inputF_(in) to the output c_(j) such that the output is according to theother of said formulas directs according to a simplified version of thesecond of said formulas:

    c.sub.j =F.sub.in if p.sub.0 (s.sub.0 ⊕x.sub.0)⊕(1-p.sub.0)(s.sub.0 ⊕x.sub.0)(w.sub.0j ⊕y.sub.0)⊕a.sub.0j =p.sub.1 (s.sub.1 ⊕x.sub.1)⊕(1-p.sub.1)(s.sub.1 ⊕x.sub.1)(w.sub.1j ⊕y.sub.1)⊕a.sub.1j and c.sub.j =1-F.sub.in otherwise.


14. The adder-subtractor device of claim 1, wherein:the nonnegativeinteger values for the parameters are such that s₀ ⊕x₀ =0 and p₀ =p₁ =1,so as to compute a result c for a simplified version of the expressionc=±a₀ ±a₁, the simplified version being c=a₀ ±a₁, such that theplurality of switches, between the lines, for directing to the forwardoutput F_(out) the bit value, directs according to a simplified versionof the first of said formulas:

    F.sub.out =a.sub.kj ⊕t if a.sub.0j =s.sub.1 ⊕x.sub.1 ⊕a.sub.1j ;

and wherein the plurality of switches also directs according to asimplified version of the second of said formulas:

    c.sub.j =a.sub.0j ⊕a.sub.1j ⊕s.sub.1-k ⊕x.sub.1-k ⊕t⊕F.sub.in.


15. The adder-subtractor device of claim 1, wherein:the nonnegativeinteger values for the parameters are such that s₀ ⊕x₀ =0 and p₀ =p₁ =1,so as to compute a result c for a simplified version of the expressionc=±a₀ ±a₁, the simplified version being c=a₀ ±a₁, such that theplurality of switches, between the lines, for directing to the forwardoutput F_(out) the bit value, directs the forward input F_(in) to theforward output F_(out) if a_(0j) ≠s₁ ⊕x₁ ⊕a_(1j).
 16. Theadder-subtractor device of claim 1, wherein:the nonnegative integervalues for the parameters are such that s₀ +x₀ =t=0 and s₁ ⊕x₁ 32 1, soas to compute a result c for a simplified version of the expressionc=±a₀ ±a₁, the simplified version being c=a₀ -a₁, such that theplurality of switches, between the lines, for directing to the forwardoutput F_(out) the bit value, directs according to a simplified versionof the first of said formulas:

    F.sub.out =a.sub.kj if a.sub.0j =1-a.sub.1j ;

and wherein the plurality of switches also directs according to asimplified version of the second of said formulas:

    c.sub.j =a.sub.0j ⊕a.sub.1j ⊕s.sub.1-k ⊕x.sub.1-k ⊕F.sub.in.


17. The adder-subtractor device of claim 1, wherein:the nonnegativeinteger values for the parameters are such that s₀ ⊕x₀ =s₁ +x₁ =0, so asto compute a result c for a simplified version of the expression c=±a₀±a₁, the simplified version being c=a₀ +a₁, such that the plurality ofswitches, between the lines, for directing to the forward output F_(out)the bit value, directs according to a simplified version of the first ofsaid formulas:

    F.sub.out =a.sub.kj if a.sub.0j =a.sub.1j ;

and wherein the plurality of switches also directs according to asimplified version of the second of said formulas:

    c.sub.j =a.sub.0j ⊕a.sub.1j ⊕F.sub.in.


18. 18. The adder-subtractor of claim 1, wherein:said line carrying saidforward input connects to a first Λ switch in said plurality of switchesfor directing, the first Λ switch being controlled by a first controlvariable signal s₀ such that if the control variable s₀ is zero, thefirst Λ switch passes the signal input on to a first 0X0 switch, butwhen the value of the control variable s₀ is 1, the output from thefirst Λ switch is applied as an input to a second Λ switch, the outputsfrom the second Λ switch are fed as inputs to the first 0X0 switch, theoutputs from the first 0X0 switch are fed as inputs to a second 0X0switch, the outputs from the second 0X0 switch are fed as inputs to athird 0X0 switch, such that one of the outputs from the third 0X0 switchis fed to the line outputting c_(j) and an other of the outputs is fedto a first forward output, when control variables are 1, 1, 0, 0, and 0,respectively, at the first Λ switch, at the second Λ switch, at thefirst 0X0 switch, at the second 0X0 switch and at the third 0X0 switchthen the signal passes to the forward output, when the control variablesare 0, 0, 0, and 0, respectively, at the first Λ switch, at the first0X0 switch, at the second 0X0 switch and at the third 0X0 switch, thesaid forward input passes to the line outputting c_(j) ; and furthercomprising a second line carrying a second forward input to a third Λswitch, and if the first control variable s₀ at the third Λ switch iszero then the second forward input is passed on to a fourth 0X0 switch,when the control variable s₀ is 1, output from the third Λ switch isapplied as an input to a fourth Λ switch, outputs from the fourth Λswitch are fed as inputs to the fourth 0X0 switch, the outputs from thefourth 0X0 switch are fed as inputs to a fifth 0X0 switch, outputs fromthe fifth 0X0 switch are fed as inputs to a first V switch, output fromthe first V switch is split with one of the outputs from the first Vswitch passing to the line outputting c_(j) and an other of the outputsfrom the first V switch passing to a second forward output line; andfurther comprising a third line which conducts a forward input value of1, connected to a fifth Λ switch, such that if the control variable s₀at the fifth Λ switch is zero, the value of 1 is passed on and is splitso that the value 1 is an input to a second V switch and value of 1 isan input to a third V switch, but when the control variable s₀ at thefifth Λ switch is 1, output from the fifth Λ switch is applied as aninput to a sixth Λ switch such that two outputs from the sixth Λ switchare each split so that both are fed as inputs to the second V switch andas inputs to the third V switch, and output from the second V switch isapplied as an input to a seventh Λ switch, and outputs from the seventhΛ switch are fed as inputs to a fourth V switch such that, when controlvariables are 0 and 1, respectively, at the fifth Λ switch and at thesecond V switch, then the value of 1 is the input to the seventh Λswitch, but when the control variables are 1, 1, and 0, respectively, atthe fifth Λ switch, at the sixth Λ switch, and at the second V switch,the value of 1 is the input to the seventh Λ switch, and further, outputfrom the second V switch is input to the seventh Λ switch, which has twooutputs fed as inputs to a fourth V switch, such that, when the controlvariable for the seventh Λ switch is different from the control variablefor the fourth V switch, the output from the second V switch is passedon to the forward output; the output from the third V switch is an inputto an eighth Λ switch, such that when the control variables are 0 and 0,respectively, at the fifth Λ switch and at the third V switch, the valueof 1 is input to the eighth Λ switch, and when the control variables are1, 1, and 1, respectively, at the fifth Λ switch, at the sixth Λ switch,and at the third V switch, the value of 1 is the input to the eight Λswitch, two outputs from the eighth Λ switch are fed as inputs to afifth V switch, such that output from the third V switch is passed on tothe second forward output if the control variable for the eighth Λswitch is equal to the control variable for the fifth V switch; whereinthe first Λ switch, the third Λ switch, and the fifth Λ switch arecontrolled by the control variable s₀ ; the second V switch, the first0X0 switch, the fourth 0X0 switch, and the third V switch are controlledby the control variables a_(0j) ; the seventh Λ switch, the second 0X0switch, the fifth 0X0 switch, and the eighth Λ switch are controlled bythe control variable s₁ ; and the fourth V switch, the third 0X0 switch,the first V switch, and the fifth V switch are controlled by controlvariable a_(1j).
 19. The adder-subtractor of claim 18, wherein:if j=1the jth device receives from the line carrying the input w_(0j) =0, thejth device receives from the line carrying the first forward input avalue of 1 if s₁ is 1, and further comprising a second forward inputline carrying a value of 1 if s₁ is 0, and a second forward output, thejth device further comprises a line carrying an output w_(0j) connectedto the plurality of switches for directing, and if j≧2 said forwardinputs to the jth device are fed from the j-1th device forward outputsand the line carrying the input w_(0j) to the jth device is feed fromthe line carrying the w_(0j-1) output from the j-1th device; andwherein: each said jth device is arranged so that a last jth device, asecond to the last jth device, and a third to the last jth device eachreceive identical values, respectively, on the line carrying the inputa_(0j) and the line carrying the input a_(1j), the output c_(j) on theline from the last jth device also represents a sign of the result; andfurther comprising plurality of switches for determining whether theresult has a value out of a range, the plurality of switches fordeterming comprising: the line carrying the output c_(j) from the secondto the last jth device is input to a first 0ON switch controlled by theoutput c_(j) from the third to the last jth device and output from thefirst 0ON switch is input to a last Λ switch controlled by the outputc_(j) from the last jth device, such that when the output c_(j) from thethird to the last jth device is 1, the last Λ switch passes output to aline that represents underflow and second output from the last Λ switchrepresents overflow; and the line carrying the output c_(j) from thethird to the last jth device is input to a second 0ON switch controlledby the output c_(j) from the second to the last jth device such thatwhen the output c_(j) from the second to the last jth device is 0, thesecond Λ switch passes output to a line that represents the overflow.20. The adder-subtractor of claim 1, wherein:if j=1 the jth devicereceives from the line carrying the input w_(0j) =0, and comprising asecond forward input line carrying the first bit 1 if s₁ is 1, andcarrying the second bit 1 if s₁ is 0, and if j≧1 the jth device receivesfrom the line carrying the first forward input a mix of a first bit 1and a second bit 1, and further a second forward output, the jth devicefurther comprises a line carrying an output w_(0j) connected to theplurality of switches for directing, and if j≧2 the second forward inputto the jth device is fed from the j-1th device forward output and theline carrying the input w_(0j) to the jth device is fed from the linecarrying the w_(0j-1) output from the j-1th device; and wherein: eachsaid jth device is arranged so that a last jth device, a second to thelast jth device, and a third to the last jth device each receiveidentical values, respectively, on the line carrying the input a_(0j)and the line carrying the input a_(1j), the output c_(j) on the linefrom the last jth device also represents a sign of the result; andfurther comprising: a plurality of switches for determining whether theresult has a value out of a range, the plurality of switches fordetermining comprising: the line carrying the output c_(j) from thesecond to the last jth device is input to a first 0ON switch controlledby the output c_(j) from the third to the last jth device and outputfrom the first 0ON switch is input to a last Λ switch controlled by theoutput c_(j) from the last jth device, such that when the output c_(j)from the third to the last jth device is 1, the last Λ switch passesoutput to a line that represents underflow and second output from thelast Λ switch represents overflow; the line carrying the output c_(j)from the third to the last jth device is input to a second 0ON switchcontrolled by the output c_(j) from the second to the last jth devicesuch that when the output c_(j) from the second to the last jth deviceis 0, the second Λ switch passes output to a line that represents theoverflow.
 21. The adder-subtractor of any one of claims 1-20, wherein atleast some of the lines are electrically conducting lines.
 22. Theadder-subtractor of any one of claims 1-20, wherein at least some of thelines are optically conducting lines.
 23. The adder-subtractor of anyone of claims 1-20, wherein all said c_(j) outputs are obtained oneclock cycle by setting all said switches during said one clock cycle.24. The adder-subtractor of claim 3, wherein:said adder-subtractordevice is comprised of at least three of said jth devices and the outputc_(j) from the last, second to last, and third to the last of the jthdevices are conveyed to means for comparing to produce an output signalrepresenting overflow.
 25. The adder-subtractor of claim 7, wherein:saidadder-subtractor device is comprised of at least three of said jthdevices and the output c_(j) from the last, second to last, and third tothe last of the jth devices are conveyed to means for comparing toproduce an output signal representing overflow.
 26. A method for makingan adder-subtractor device, the method comprising the steps asfollows:inserting any nonnegative integer value less than 2 inparameters k, p₀, p₁, t, x₀, x₁, y₀, and y₁ of formulas specifying anoutput c_(j) and a forward output F_(out) with respect to a forwardinput F_(in) : ##EQU27## to obtain a representation of switching for ajth device for each bit position j, to compute a result c for anexpression c=±a₀ ±a₁ where a₀ and a₁ are binary numbers; connecting aplurality of switches in each said jth device according to saidrepresentation so that each said jth device includes: (1) a linecarrying an input corresponding to the s₀ parameter, representing the x₀parameter when the sign at the a₀ number in the expression is positiveand representing 1 minus the x₀ parameter when the sign at the a₀ numberin the expression is negative; (2) a line carrying an inputcorresponding to the a_(0j) parameter, representing a jth digit of thea₀ number; (3) a line carrying an input corresponding to the s₁parameter, representing the x₁ parameter when the sign at the a₁ numberin the expression is positive, and representing 1 minus the x₁ parameterwhen the sign at the a₁ number in the expression is negative; (4) a linecarrying an input a_(1j) representing a jth digit of the a₁ number; (5)the jth device further including a line carrying an input for theparameters w_(0j) =1-y₀ when s₀ =1-x₀ and if any previous bit positionof the a₀ number is 1, and w_(0j) =y₀ when s₀ =1-x₀ and there is no 1 onany previous bit position, and w_(0j) has a nonnegative integer valuethat is less than 2 when s₀ =x₀ ; (6) the jth device further including aline carrying an input for the parameters w_(1j) =1-y₁ when s₁ =1-x₁ andif any previous bit position of the a₁ number is 1, and w_(1j) =y₁ whens₁ =1-x₁ and there is no 1 on any previous bit position, and w_(1j) hasa nonnegative integer value that is less than 2 when s₁ =x₁ ; (7) atleast one line carrying the forward input F_(in) ; (8) at least one linecarrying the forward output F_(out) ; (9) a line carrying the outputc_(j) representing a jth digit of the result from computing theexpression ±a₀ ±a₁ ; and (10) a plurality of switches, between thelines, for directing the forward input F_(in) to the output c_(j) suchthat the output is according to said representation corresponding to theformula for c_(j), the plurality of switches also for directing to theforward output F_(out) a bit value, according to said representationcorresponding to the formula for F_(out).
 27. An adder-subtractor devicemake by the process set forth in claim 26.